WireWorld has 1 type of wire, WireWorldRgb adds two more types of wire, for a total of three types: red, green and blue.

Similar to WireWorld, particular combinations of neighbor heads (from the 8 possible neighbors) make a wire become head, heads become tails, and tails become wire again. Wires, heads and tails always remain within their color (green head becomes green tail, etc...).

The rules to become head are:

- Red wire becomes red head if it touches either 1 or 2 red heads, or 1 or 2 blue heads, and ignores green heads.
- Green wire becomes green head if it touches either exactly 1 green head, or exactly 1 red head, and ignores blue heads.
- Blue wire becomes blue head if it touches either exactly 2 blue heads, or exactly 1 green head, and ignores red heads.

With these rules, red behaves like original WireWorld, and since the numerical values of those cell types match, regular WireWorld maps can be loaded into WireWorldRgb. Each color ignores one other color, so in WireWorldRgb, signals can stay within their color or flow through different colors in the cycle red->green->blue->red->... but not in the opposite direction, like diodes.

New thanks to these rules is the ability to create more compact logic gates, and have everything (logic gates, wire crossings, RS latches, half adders, full adders, ...) work with 3-cycle logic, the shortest possible since a signal takes at least 3 cells (head, tail, wire). In addition, each of those introduces zero delay compared to signal going through straight wire.

To make compact fast logic gates, OR can be made with 2 blues to red, AND can be made with 2 blues to blue, ANDNOT can be made with a blue and green to blue, XOR can be made either with 2 reds to green, or with 2 greens to blue, NOT can be made with a 3-cycle "rgb" clock on 1 input of a XOR.

The small wire crossing can be made like this:

g "X->" rrrr brrrr "->Y" g "Y->" rrrr brrrr "->X" g

The small half adder can be made like this (c = carry, s = sum):

rg "a->" rrrrr brrrr "->c" gb "b->" rrrrr rrrrr "->s"

A 3-cycle serial (infinitely streaming) full adder, RS latch based, can be made like this (the capital S is a red tail, the capital G a green head, those are part of a NOT gate clock):

rrr r rg r b brrrrrr rrrrrr rrr SG g gb r b g rrrrrr br rrg bg rg r r r rrgb r

To run in Golly, which is a great cellular automaton simulation program that includes WireWorld as well, download the files below, place WireWorldRgb.rule in the Rules directory, and the mc file in the Patterns directory.

The full specification can be found in the comments in WireWorldRgb.rule. The map wireworldrgb.mc shows how to make logic gates, streaming adders, wire crossings and flip flops.

Screenshot:

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